Relationship between Phase Noise and Jitter
Phase Noise and Jitter are both ways of describing the stability of an oscillator. Phase Noise describes the stability in the frequency domain whilst jitter describes the stability in the time domain. The choice of which domain to consider the oscillators stability is usually application dependant. RF (Radio Frequency) Engineers working in Radar, Base Station design etc. will be interested in Phase Noise as poor Phase Noise performance will affect up/down conversions and channel spacing. Digital Engineers working in Time Division Multiplexing (the majority of modern Telecoms infrastructure) will be interested in jitter as poor jitter performance will result in network slips and excessive re-send traffic.
Relationship Between PN and Jitter
Phase Noise and Jitter in Crystal Oscillators
Before we can cover the sources of Phase Noise / Jitter in Crystal Oscillators we need to de-mystify some of the wording associated with the measurement, so let’s start with a simple description of Phase Noise and Jitter.
IC Crystal Oscillator Circuits
The majority of ICs with built in crystal oscillator circuits use the Gated Pierce design where the oscillator is built around a single CMOS inverting gate. For oscillator applications this is usually a single inverting stage comprising one P channel and one N channel enhancement-mode MOSFET, more commonly known in the digital world as an Un-Buffered Inverter (see Fig.1). It is possible to use a Buffered Inverter (usually comprising three P-N MOSFET pairs in series) but the associated gain of many thousands will lead to a potentially less stable finished oscillator.
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